![]() The OREAD and HREAD procedures come in two overloaded flavors for each of the supported output types. The code below shows the definitions of the procedures that are relevant for us, they are only available in VHDL-2008 and newer revisions. For simplicity, we are going to skip octal reads in this article and focus on how to read hexadecimal and binary values from a text file. The methods for reading octal and hexadecimal values are quite similar, the octal values are merely a subset of the hexadecimals. VHDL-2008 defines the OREAD, HREAD, and BREAD procedures for extracting octal, hexadecimal, and binary values from a LINE object. The LINE type is simply an access type to a string, a pointer to a dynamically allocated string object. Type LINE is access STRING - A LINE is a pointerĪlthough the class of the LINE parameter isn’t explicitly specified in the prototype declaration of READLINE, it’s a variable because that’s the default class for inout parameters. Procedure READLINE (file F: TEXT L: inout LINE) The prototype declaration of the READLINE procedure and the LINE type taken from the VHDL standard specification is shown below. The procedure takes two arguments, the file name as a constant input and the parsed line of text as an inout variable. To read a line of text we use the READLINE procedure from the TEXTIO package. We will store the RAM data in an ASCII file where one line of text corresponds to a memory slot. We can simply go ahead and use the TEXTIO package in the header of our VHDL file like this: The standard library is always loaded therefore, we don’t have to import it explicitly with the library keyword. The subprograms and types needed for reading and writing external files in VHDL are located in the TEXTIO package. Stimulus file read in testbench using TEXTIOīMP file bitmap image read using TEXTIO READLINE, LINE, HREAD, OREAD, and BREAD This blog post is part of a series about using the TEXTIO library in VHDL. Of std_logic_vector(ram_width - 1 downto 0) Type ram_type is array (0 to ram_depth - 1) The examples throughout this article will assume that the following constants and RAM type have been declared at the start of the declarative region of the VHDL file. After all, RAM and ROM are the same thing in FPGAs, ROM is a RAM that you only read from. This is also a good way to create a ROM (read-only memory) in VHDL. A convenient way to populate block RAM with initial values is to read binary or hexadecimal literals from an ASCII file. ![]()
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